There are gradients in the transistor values of switching transistors within a DAC array. These gradients are typically caused by process inaccuracies, e.g., fabrication inaccuracies such as well-proximity effect, length of diffusion effect, faulty oxide irregularities, poor polysilicon etching and/or implant non-uniformities. Such process gradients can cause normally identical transistors to pass different amounts of current through one or more of the transistors in the DAC switching array.
In high resolution DACs, the effects of these gradients can become a limiting factor of linearity performance, including differential-nonlinearity (DNL) and integral-nonlinearity (INL). Numerous techniques have been proposed to alleviate this problem by either employing specific switch sequences designed to overcome the gradient effect or by using random switch sequences. Present technologies have focused on general purpose DACs designed to have improved linearity uniformly over the entire code range of the DAC. However chip-area and/or power consumption will increase in order to improve linearity over the entire code range of the DAC.
While many applications require DACs with uniform linearity performance across the entire input code range, some applications only require good linearity performance in a certain input code range while allowing worse linearity in other code ranges. For example, in advanced communications applications, orthogonal frequency division multiplexing (OFDM) is often used. A DAC used in a OFDM communications system need only have good linearity performance in the middle code range, while worse linearity is acceptable on either side of this middle code range.